1. Field of the Invention
The present invention relates to a data reading circuit in a semiconductor memory device, and more particularly, to such a circuit adapted to realize an improved static random access memory which can operate at a speed of, for example, 25 ns to 35 ns.
2. Description of the Related Art
In general, in a data reading circuit of the prior art static random access memory (static RAM), when a signal from a data bus line is input, a sense amplifier senses the signal and delivers a sense output signal. The sense output signal is input to a first output transistor as a first sense data signal through a first set of inverters, and is input to a second output transistor as a second sense data signal through a second set of inverters. An output stage is composed of the above-noted first output transistor and second output transistor, which deliver the data output signals upon receipt of the first and second sense data signals.
In the above-mentioned data reading circuit, there is a first delay time from when an input signal is supplied to a sense amplifier to when a waveform of the sense output signal starts to lead or to trail, and a second delay time from when the above-mentioned sense output S.sub.OT is received to when the leading edge of the data signal starts to pass through a set of inverters. The sum of the first delay time and second delay time is regarded as the delay time for the operation.
In this case, if a gate input is given a time difference, to avoid making two of the series-connected output stage transistors simultaneously ON, the second delay time is inevitably long, and thus the problem of a reduced operational speed of the circuit arises.
In the prior art, two sense amplifiers are used and a complementary sense output is retrieved from among the sense outputs and input directly to the two series-connected output stage transistors through a set of inverters, thus obtaining the data output D.sub.OT from the output stage transistor. In the prior art data reading circuit having the above-described operation, the waveform of the complementary sense output signal is the same as in the case of one of the above-described sense amplifiers, and therefore, even in this case a problem arises in that the operation speed remains low.